Raytheon Missile Systems, Tucson, AZ.                                                                                  (4/2013 – 2/2014)

Senior Firmware Engineer (contract, 9 month), Configurable Logic Dept,

Supported preliminary design effort for an IO Adapter FPGA (Xilinx Artix 7) used on an IO Adapter card to format and forward guidance and video data to data link and telemetry subsystems, commands to Boost Vehicle.

  • Generated requirements, FPGA pinouts (Vivado design tools), and preliminary architecture for FPGA and board layout design.

Supported firmware integration and testing (VHDL and Embedded Software) of Modem FPGA on a Modem card for a RF data link transceiver system, based on Altera Cyclone 4, Max II CPLD and Nios processor. System is in production phase early 2014.

  • Verified RF communication link (ADC, DAC, 8-ary FSK, preamble, RS encode/ decode, CRC, baseband) with test station software, lab test equipments.
  • Debugged and modified VHDL to fine tune radio transmit and receive timing, SDLC communications.
  • Debugged and modified embedded C code to add features for commands structure and BIT (Built-In Test) testing.
  • Worked with UART, I2C, SPI serial interfaces for temperature, voltage monitors.
  • Worked with script-based Linux system for simulation (Modelsim), synthesis (Synplicity) and FPGA builds. Used simulation, Nios software debugger and SignalTap for debug and verification.

Boeing Network & Space Systems, El Segundo, CA.                                                             (7/2012 – 12/2012)

Senior Design Engineer (contract, 6 month), Digital ASIC/ FPGA Group

Member of a team to develop a controller SoC ASIC on 0.13um ARM/IBM process. The ASIC provides monitoring and control of Optical Transceivers used for space-based telecommunications, control applications.

  • Implemented MemBist (Memory Built-in test), microcontroller control and other logic functions using SV/ Verilog, Questa Sim.
  • Performed design verifications with SV test bench and Keil 8051 simulation/ assembly tools for the Synopsys DW8051 microcontroller core used as SoC for the ASIC.
  • Generated top level net list, Scan, ATPG using Synopsys DC compiler.

Applied Signal Technology, Inc., Sunnyvale, CA. (now, Raytheon Applied Signal Tech)               (1999-2012)

Senior Hardware Engineer, Broadband Communication Systems Div.

Developed digital receiver FPGA (Xilinx Virtex6) on a Wideband Digital Receiver board to implement various components of a radar signal processing application for company’s next generation surveillance radar product.

  • Implemented DSP block from a Matlab representation, FFT (8K) and IFFT (dual channel @250MHz to support sample rate), overlap-save buffering architecture (VHDL/ SystemVerilog/Verilog, Xilinx and board vendor IP cores).
  • Implemented interface and buffer logic to ADC front end (1.2 Gig samples) and PCIE back end with AXI bus stream interface, AXI bus local memory control, output data selection and packetized interface logic.
  • Used Modelsim/ Synplify and Xilinx 13.2 tools for builds. Supported all phases of development, system and software integration. (This work was done for another division of the company).

Completed miscellaneous various design enhancements on existing telecommunication and packet processing FPGAs (Xilinx Virtex4) to support continuing customer requirements.

  • Redesigned to allow selections of byte synchronous E1 timeslot groups within a TU12 structure of a STM-1 SDH frame, “Ethernet Stripper” module to strip IP or MPLS packets out of a LAPS (Link Access Procedure for SDH) frame. Re-built and successfully tested FPGA builds with new capabilities.

Developed Altera Cyclone 4 FPGA design on a development board to implement an Active Noise Cancelling system for company’s IR&D work on new product.

  • Implemented Audio Codec’s ADC and DAC interfacing, memory control and I/O buffer infrastructure for Nios processor. Embedded an adaptive filter VHDL implementation. (VHDL/ Verilog)
  • Built FPGA, modified and integrated embedded software within Quartus 10.1 tools environment. Successfully demonstrated audio nulling results in audio labs.

FPGA lead engineer to develop company’s Content Collection Processor with 2xSTM-16 inputs and 10GigE output hosted on a Vixtex6 mezzanine and a Virtex5 PCIE main board.

  • Completed the first phase of the design to implement an embedded PowerPC and 400MHz DDR2 1G DIMM memory with Xilinx MIG tools, local bus memory interface, PCIE register interface. Generated BSP (board support package) and successfully booted embedded Linux.

Team member to develop a high capacity telecom processing FPGA (Xilinx Virtex5). The FPGA receives 2xSTM-16 (2048 E1) input data stream via 10GigE port (XAUI), performs look-up, signaling detection and routing data to 1GigE output link.

  • Performed bus architecture, design tradeoffs and implemented embedded PowerPC design, local memory bus, PCI interface for control and boot, RLDRAM controller IP from Northwest Logic (upgraded to Low Power DDR memory using modified Xilinx DDR controller for new board), GigE Ethernet (TEMAC 1000BaseX).
  • Created BSP package for software development and embedded Linux boot. Also developed lower level VHDL modules to support telecom processing functions at 160MHz system clock (parallel/ pipelined design).

Responsible engineer to port FPGA design from Xilinx Virtex2 Pro to Virtex4 for an upgraded high speed data processing system. The FPGA aggregates multi data input streams to buffer data to DDR memory, encrypts and packetizes data for outputting.

  • Modified FSM interface logic to Northwest Logic DDR memory controller (from Sdram) with new DDR features.
  • Implemented new packet format and framing logic and data output using TCP/IP GigE Ethernet (TEMAC RGMII) with DMA on embedded PowerPC405 processor. An alternate hardware dedicated UDP output data path was designed but not implemented. Higher throughput enhancement was demonstrated.

Lead engineer for one of the 2 FPGA designs used on the company’s new digital channelized wideband receiver board that employs 4 Altera Stratix II FPGAs. The board processes 6 IF inputs (500 MHz processing bandwidth), part of the company’s system entry into the ESM (Electronic Support Measures) market. The system was designed to have widest range, low size, power and weight, and high probability of intercept. Implemented VHDL to:

  • Interface to 6 IF channels data in parallel/ pipelined design running at 160MHz system clock.
  • Perform signal measurements such as amplitude, phase, frequency, and time of arrival.
  • Run a processing schedule and process command and control via Ethernet, format and buffer output radar pulse data.
  • Provide Nios infrastructure for software development with embedded MicroOS.

Worked with SW engineer to design a zero-copying, low overhead architecture to make use of an MAC IP and Nios processor to increase the needed Ethernet bandwidth (first with TCP/IP then with UDP). The system has been tested both on ground and in flights. (This work was done for another division of the company)

Team member to implement signal processing of various telecommunications protocols (SS5, SS7, T30 Fax Scan with input data rate of STM-1/STM-4) in hardware on an Altera Stratix I platform to demonstrate high performance system with low size, weight and power. The successful demonstration led to major program win for company.

  • Developed VHDL modules for embedded Nios I processor infrastructure.
  • Developed VHDL modules for Fax Processing, HDLC, channel remapping, look-up and routing capability.
  • Performed trade studies of power and performance evaluation by porting FPGA build to Altera and Xilinx Virtex II Pro platforms for FPGA architecture selection of new board design.
  • Involved in designing a new data processing board with Altera Stratix II FPGAs, schematic design, pin-out verification, analyzing timing, board placement review, resource estimate and allocation.

Team member to develop packet processing FPGAs (Virtex 2000E @100MHz) for company’s first generation packet processing system on both company’s processor board, and on a custom daughter card hosted on a third party processor (Motorola G4) board to process IP packets at STM4 (4xSTM1) rate in SDH, PDH, ATM, VC4-POS (Packet-Over-Sonet) formats.

  • Developed SDRAM controller/ Arbiter logic.
  • Developed PowerPC 60X Bus control logic.
  • Developed PCI interface, Data Path (Byte HDLC, Bit HDLC processing, ATM Physical Layer).

Lead engineer to develop telecom processing FPGAs (Lucent ORCA) to process multichannel E1 and DS1 digital voice grade channel data for a TMS DSP-based board.

PREVIOUS EXPERIENCE

ASIC Design Engineer, ASIC Design Center, Lockheed Missiles & Space Company, Sunnyvale, CA.

Sr. Engineer, Digital Systems Group, The Charles Stark Draper Laboratory, Cambridge, MA.